1. Field of the Invention
The present invention relates generally to the field of power semiconductor device and, more particularly, to a static induction semiconductor device with a distributed main electrode structure which is improved in the device turn-off performance through substantial reduction of the minority carrier storage time, the device fall time and the quantity of gate electrode pull-out charges that are factors important to the turn-off switching performance of the device. The invention also pertains to a static induction semiconductor device with a static induction main electrode shorted structure which permits reduction of the quantity of charges that are pulled out of the gate electrode when the device is turned off.
2. Description of the Prior Art
There have heretofore been proposed a variety of structures intended to improve switching performance of static induction (hereinafter abbreviated to SI) semiconductor devices. FIG. 43 shows in section the structure of a first prior art example that is proposed by Nishizawa and Tamamushi in Japanese Patent Public Disclosure No. 91474/89 to reduce the input capacitance between the gate and the source or between the gate and the cathode and enhance the efficiency of electron injection from the source or cathode region in an SI transistor or thyristor with a buried gate structure. In FIG. 43, reference numeral 1 denotes an n.sup.- -type high resistivity layer, 3 an anode or drain region, 4 gate regions, 5 channel regions and 11 cathode or source regions.
In the first prior art example, a semiconductor region that serves as a cathode or source is provided only above a channel defined by buried gates therebetween to reduce the capacitance between the gate-cathode or gate-source capacitance to thereby increase the device switching speed with no reduction of the channel current.
Since the semiconductor region of high impurity concentration, which serves as the cathode or source region, is provided only above the channel region defined by the buried gate regions therebetween, the junction capacitance between the gate and cathode or source regions is smaller than in the past. Accordingly, a time constant that is defined by the product of the gate resistance and the junction capacitance is smaller than before and the gate-cathode or gate-source voltage reaches the gate region apart from a gate electrode more rapidly than before. This reduces the turn-on time and the turn-off time, and hence permits high-speed switching of the device.
A second prior art example is shown in FIG. 44, which is a sectional view of an SI thyristor disclosed by Kawamura and Morikawa in Japanese Patent Public Disclosure No. 257266/90. In FIG. 44, reference numeral 1 denotes an n.sup.- -type high resistivity layer, 3 p.sup.+ -type anode regions, 4 gate regions, 6 n.sup.+ -type short-circuit layers, 7a a cathode electrode, 7b a gate electrode, 7c an anode electrode, 11 n.sup.+ -type cathode regions and 13 p.sup.+ type short-circuit regions. The structure depicted in FIG. 44 is intended to provide an SI thyristor with a shorted cathode structure which is excellent in its turn-off characteristic, current carrying capacity and breakdown voltage, by increasing the cathode area utilization factor.
The SI thyristor of the second prior art example, which has the n.sup.+ -type cathode regions 11 and the p.sup.+ -type short-circuit regions 13 formed in one main surface of the n.sup.- -type high resistivity layer (an n.sup.- -type base region ), is characterized by a construction in which the p.sup.+ -type gate regions 4 are buried in the n.sup.- -type base region 1 side by side in parallel to the said main surface thereof, the n.sup.+ -type cathode regions 11 are each formed opposite the channel region defined by the p.sup.+ -type gate regions therebetween and the p.sup.+ -type short-circuit regions 13 are disposed partly opposite the p.sup.+ -type gate regions 4.
That is, the p.sup.+ -type gate regions 4 are provided as buried regions, the p.sup.+ -type short-circuit regions 13 are formed above the gate regions 4, and the regions defined between the short-circuit regions 13 form the n.sup.+ -type cathode regions 11, which serve as main current paths at the cathode side. This structure provides increased device area utilization factor.
FIG. 45 is a sectional view showing, as a third prior art example, an SI thyristor disclosed by Muraoka in Japanese Patent Public Disclosure No. 152063/85. Reference numeral 1 denotes an n.sup.- -type high resistivity layer, 3 second high concentration regions (p.sup.+ -type anode regions), 4 gate regions, 7a a cathode electrode, 7b a gate electrode, 7c an anode electrode, 11 first high concentration regions (n.sup.- -type cathode regions), 12 a support electrode, and 14 and 14' insulating regions. With such a structure as shown in FIG. 45, the p.sup.+ -type buried gate regions 4 lessens the effect of a parasitic bipolar transistor formed in a region defined by the cathode and anode regions between them, thereby preventing retriggering of the device by the parasitic bipolar transistor, enhancing the dv/dt capability of the device immediately after its turn-off and improving the gate loss at turn-on during high-frequency operation.
The above-mentioned third prior art example is intended to offer an SI thyristor of a novel construction that is free from the parasitic bipolar transistor effect and remarkably high in the yield rate of production.
To attain such an object, in the third prior art example, the above-mentioned first high concentration regions 11 may be formed so that their junction is shallow in the regions directly above the buried regions 4 and deep in the other regions.
This structure allows the dv/dt capability just after turn-off to be held high as required, permits reduction of the gate loss at turn-on during high-frequency operation and appreciably raises the yield rate of production.
In this third prior art example, the second high concentration regions 3 may be formed so that their junction is shallow in the regions directly below the buried regions 4 and deep in the other regions. This further increases the dv/dt capability.
It is also possible to form an insulating layer between the region directly below the gate region and the anode electrode, this further enhances the above-noted effects.
In the same structure as shown in FIG. 44 of the second prior art, the inventors of this application found out a phenomenon that when the device is turned off, the p.sup.+ -type buried gate regions 4 and the p.sup.+ -type short-circuit regions 13 get shorted and extra holes are injected from the p.sup.+ -type short-circuit regions 13 into the n.sup.- -type high resistivity region 1, increasing the quantity of charges that are extracted from the gate electrode 7b. This leads to an adverse effect that the turn-off time increases.
The SI thyristor structure of the first prior art example is intended primarily to reduce the parasitic capacitance, but since the first prior art example makes no reference to the arrangement of the cathode electrode, the flow of holes at turn-on and turn-off are unconfirmed, and it, too, makes no mention of the effect of reducing the quantity of holes extracted according to the present invention as described later on. The third prior art example also aims to lessen the effects of a parasitic bipolar transistor and a parasitic diode and makes no mention of the flow of holes at turn-on and turn-off; hence, the effect of reducing the quantity of holes that are extracted at turn-off is not found.
Moreover, the inventors of this application have found, by experiment, that in an SI device with a buried gate structure, buried diffused layers (p.sup.+ -type gate regions) directly below an n.sup.+ -type cathode region are formed more rapidly and wider during the same diffusion period than those formed just under a region where no n.sup.+ -type cathode region is formed. FIG. 46 is a schematic sectional view of the SI device, for explaining the above. As shown, p.sup.+ -type buried regions 4 just under an n.sup.+ -type cathode region 11 spread wider than those formed not directly under it. As is evident from FIG. 46, the distance between the gate and cathode varies according to the position of the respective buried region. It is also clear that such variations in the distance between the gate and cathode is liable to cause dispersion in the breakdown voltage between the p.sup.+ -type gate region and the n.sup.+ -type cathode region in each segment forming the SI thyristor. Since the p.sup.+ -type gate region just under the n.sup.+ -type cathode region, in particular, spreads quickly toward the cathode region as well, the substantial distance between the gate and cathode decreases and the breakdown voltage there between is determined accordingly. Hence, it is necessary to control the setting of conditions for obtaining a predetermined breakdown voltage and suppress variations in the breakdown voltage in respective segment and among segments.
In the prior art examples described above, too, there is not proposed any particular cathode layout pattern aimed to suppress the dispersion in the breakdown voltage that is caused by the above-mentioned variations in the diffusion of individual buried regions. The reason for this is that the cathode region in the prior art is usually formed uniform and homogeneous unlike a nonuniform, inhomogeneous distributed structure proposed by the present invention.
FIG. 47 shows schematic longitudinal, cross-sectional and top views of a unit segment of the SI thyristor with a conventional buried gate structure in which the cathode region is formed uniform and homogeneous.
As is evident from FIG. 47, the cathode electrode 7a is disposed substantially all over the n.sup.+ -type cathode region 11 without lying off its edge, and hence is not in touch with the n-type epitaxial layer 10. FIG. 48 shows an typical switching waveform of such a conventional SI thyristor during 1200 V-100 A switching conditions. Reference character I.sub.T denotes an anode current, V.sub.D an anode voltage, I.sub.GP a gate peak current, I.sub.RG a gate current and V.sub.RG a gate voltage.
FIG. 49 through 52 schematically show how holes and electrons move or migrate in the unit cell structure of the SI thyristor during an on-state period t.sub.0, minority carrier storage period t.sub.1, a fall period t.sub.2 and a tail period t.sub.3 in the waveform of FIG. 48, respectively. White circles indicate holes and black circles indicate electrons.
In the on-state period t.sub.0, even if the application of a forward bias between the gate and cathode is not continued, electrons inject from the cathode to the anode, whereas holes flow from the anode to the cathode via the channel or gate (FIG. 49). When a reverse bias is applied between the gate and cathode, the hole current from the anode flows into the gate and holes distributed in the channel near the gate and in the n-type epitaxial layer between the gate and cathode are also drifted by the reverse biased electric field into the gate. On the other hand, electrons keep on flowing from the cathode to the anode, but as the potential barrier height in the channel increases owing to the reverse gate, some of the electrons flow back into the cathode region. In FIG. 50, reference character "iha" the hole current from the anode to the cathode in the minority carrier storage period t.sub.1, "Qha" the quantity of its charges, "ihb" the hole current from the vicinity of the channel and from the n-type epitaxial layer between the gate and the cathode into the gate, "Qhb" the quantity of its charges, "ie" the electron current flowing back into the cathode region and "Qe" the quantity of its charges.
The quantity of charges extracted from the gate at turn-off under 1250 V-300 A switching conditions was Qha+Qhb+Qe=456.6(.mu.C). This value was obtained from a switching waveform of the conventional SI thyristor under L inductive load switching conditions described later with reference to FIG. 54.
When a depletion layer spreads between the individual gate regions and a sufficiently high potential barrier is formed in the channel, the injection of electrons from the cathode region stops and the switching waveform enters the fall period t.sub.2 (FIG. 51).
FIG. 52 shows how a tail current flows in the tail period t.sub.3.
It is a problem of the conventional SI thyristor that the quantity of charges to be extracted from the gate, Qha+Qhb+Oe, is very large. An important problem, in particular, is that the quantity of charges, Qhb, is large. The large quantity of charges to be pulled out of the gate inevitably calls for a bulky gate driver and also constitutes a serious obstacle to the speeding up of the switching operation of the SI thyristor. It may sometimes form the cause leading to the destruction of the device with an increase in a gate loss at turn-off under high temperature conditions.